Core Concepts

Combinational vs. Sequential

One of the primary goals of vctx is to have intuitive syntax when working with immediate logic and clocked logic.

:= Combinational (Wires): Represents an immediate connection. Used for logic that reacts instantly to input changes.
<= Sequential (Registers): Represents a clocked update. Used for logic that changes state only on the next clock edge.
= Declaration: Used only for defining initial values or reset states during variable declaration.

Global Clock and Reset

vctx simplifies hardware design by assuming a standard synchronous model:

Single, global clock: clk
Single, global reset: rst

You do not need to manually route these signals; the compiler handles them automatically.

Example

component LogicDemo(in switch: bool, out led: bool) {
    // Continuous connection: reacts instantly
    wire combined: bool
    combined := switch & true

    // Sequential state: updates on clock edge
    // Reset value (0) is automatically applied via global rst
    reg state: u1 = 0
    state <= ~state

    led := state as bool
}