Skip to content
vctx

FPGA Synthesis

Complete FPGA Flow

Section titled “Complete FPGA Flow”

Because vctx compiles to standard SystemVerilog, it works seamlessly with open-source FPGA toolchains.

Step-by-Step Example (Tang Nano 9K)

Section titled “Step-by-Step Example (Tang Nano 9K)”

Verify your design

Section titled “Verify your design”
Terminal window
vctx check examples/blinky.vctx
vctx test examples/blinky.vctx

Generate SystemVerilog

Section titled “Generate SystemVerilog”
Terminal window
vctx sv --top examples/blinky.vctx
# Creates: build/Blinky.sv

Synthesize (Yosys)

Section titled “Synthesize (Yosys)”
Terminal window
yosys -p "read_verilog -sv build/Blinky.sv; \
          synth_gowin -top Blinky -json build/blinky.json" \
      -l build/synthesis.log

Place & Route (nextpnr)

Section titled “Place & Route (nextpnr)”
Terminal window
nextpnr-himbaechel \
    --device GW2A-LV18PG256C8/I7 \
    --json build/blinky.json \
    --write build/blinky_routed.json

Pack Bitstream

Section titled “Pack Bitstream”
Terminal window
gowin_pack -d GW2A-18C -o build/blinky.fs build/blinky_routed.json

Program

Section titled “Program”
Terminal window
openFPGALoader -b tangnano9k build/blinky.fs

Need an offline copy? Download Full Manual (.md)